Please provide me the power up sequence timing diagram for the BSC9131

[manjanagoudapat]

Hi

Please provide me the power up  sequencing timing diagram for BSC9131. In datasheet it is mentioned all power should be stable within 50ms,

According to datasheet

Power Sequencing

The device requires its power rails to be applied in a specific sequence in order to ensure proper device operation. These

requirements are as follows for power up:

1. VDD, VDDC, AVDD (all PLL supplies)

2. LVDD, BVDD, CVDD, OVDD, X1VDD, X2VDD, GVDD

how much delay should be provided between 1 and 2 group.

Thanks

[r8070z]

Have a great day,

Delay is not specified as some fixed value +/- tolerance. The datasheet requires that 2 group members should start with some Delays which Ensure that all member of 1 group reach 90% of their nominal value before any member of 2 group reaches 10% of its nominal value. And all they should reach nominal values within 50 ms.

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[manjanagoudapat]

Hi Serguei Podiatchev,

Thank you for the reply.

Is GVDD(DDR contoller I/O voltage) should be part of the sequence? According to datasheet,

In order to guarantee MCKE low during power-up, sequencing for GVDD is required. If there is no concern about any

of the DDR signals being in an indeterminate state during power-up, the sequencing for GVDD is not required.

without GVDD sequencing will it damage the chip?

Regards

[r8070z]

Yes GVDD(DDR contoller I/O voltage) should be part of the sequence if DDR memory chips connected to the device.