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MKE04 interrupt latency

Question asked by David Hollinrake on Jul 14, 2015
Latest reply on Jul 22, 2015 by David Hollinrake

I am using the MKE04Z8VFK4.  The interrupt latency that I measure is more than the 15 cycles that the ARM M0+ documentation specifies as the best case interrupt latency, assuming zero wait state memory.  I have simple test code that uses FTM2 channel 0 to interrupt on the rising edge of an input signal and the FTM2_Isr() toggles an output pin using single cycle FPGIOA port.  The assembly code listing for the output pin toggle shows it to be 6 clocks (4 instructions).  The interrupt latency I measure, taking into account the 6 clocks due to the output toggle, 1 clock for possible rise time error, and 15 clocks for the M0+ interrupt handling, is about 12 clocks longer that expected (or 10 clocks longer than expected if the code is running in RAM).  Does anyone know the reason for the extra clocks? 


First instruction in FTM2_Isr(): 

   FGPIO_Toggle(FGPIOA, GPIO_PTB5_MASK); /* Debug. Toggle port pin B5 when first entering interrupt */


IAR listing for FGPIO_Toggle():

   1022             FGPIO_Toggle(FGPIOA, Z_OUT_MASK);/*~ Debug. Toggle Z when first entering interrupt */

   \                     FTM2_Isr: (+1)

   \   00000000   0x2080             MOVS     R0,#+128

   \   00000002   0x0180             LSLS     R0,R0,#+6        ;; #+8192

   \   00000004   0x....                  LDR      R1,??DataTable24  ;; 0xf800000c

   \   00000006   0x6008             STR      R0,[R1, #+0]