I have a few technical questions regarding the M4 core of the i.MX6 solo X core
- I am working with the MQX 4.1.0 software for the solo X am trying to understand whyQSPI2 address 0x78000000 is used for the start of M4 core code (i.e. interrupt vector table). I am not seeing any explanation of this address determination in any of the Freescale documentation. Why is this starting halfway into the QSPI2 address space? Is this something specific to the actual SABRE-SD memory configuration? Please advise.
- I am also wondering why the MQX 4.1.0 software uses 4KB of memory at address 0x2091F000 for clock management share memory. According to Figure 8-3 in section 8.4.1 of the reference manual this memory is part of the 8K stack in OCRAM used by the system boot ROM. Is there a reason why this particular memory range was needed for this function? Could it be relocated? Is it considered acceptable because the U-boot is executing when this memory is overwritten?
- Can you please supply me with the source code for the U-boot image used to build the u-boot-sdb.imx image which is included in binary form only in the MQX 4.1.0 bundle?