My customer is trying to connect the original camera to MIPI-CSI2 interface on MCIMX6Q-SDP.
But, the video signal (YUV422 1080p@30fps) can not be acquired right.
They checked the difference of MIPI-CSI2 register between original camera (Failed) and OV5640 (Success).
Below bit was different.
Refer to 40.6.6 General settings for all blocks (MIPI_CSI_PHY_STATE) in IMX6DQRM(Rev.2).
- Original camera (Failed) --> 0x230
- OV5640 (Success) --> 0x330
Field 8 phy_rxclkactivehs
Indicates that the clock lane is actively receiving a DDR clock
Default Value: 0
Could you tell me the condition to become "phy_rxclkactivehs = 1"?