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i.MX53 ESDCTL_SDCTRL register setting

Question asked by torus1000 on Jul 12, 2015
Latest reply on Jul 13, 2015 by igorpadykov

Hi

 

Now we are debugging LPDDR2 timing for our custom i.MX53 board.
  (Please see our previous thread : https://community.freescale.com/message/533008)

 

We tried to change ESDCTL_SDCTRL for adjust delay of SDCLK.
For the bit11-8 field description on p1298 of RM shows as following: "Add sdclk0 delay of 1 delay units."

 

(Q1) How many [pSec] does 1 delay units mean?
(Q2) Does more/bigger delay improve timing margin to the CS/RAS/CAS/WE/<adr>/<dat> of DDR2 read?

 

When we write 0x00000300(SDclk0_del=2'b11) to the ESDCTL_SDCTRL with JTAG-ICE, but read value was 0x00018000.

 

(Q3) What was wrong with my writing?

 

Best Regards.

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