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How to enable cache for i.mx6 EIM

Question asked by Rinkesh Patel on Jul 9, 2015
Latest reply on Jul 10, 2015 by Rinkesh Patel

We are using LDM/STM instruction(shown below) to transfer data from i.mx6 over SRAM interface but the performance is same as no LDM/STM.

asm(

    "pld [%[address]]\n\t"

    "vldm %[address],{q0-q7}\n\t"

    "vstm %[address1]!,{q0-q7}\n\t"

    ://outputs

    :[address]"r"(array),[address1]"r"(pusAddr16)//inputs

    :"q0","q1","q2","q3","memory"//clobbers

);

 

Everyone says that cache should be enabled to achieve high performance using STM/LDM.

I am new to freescale and can someone guide me How to enable cache for i.mx6 EIM?

 

Thanks and Regards,

Rinkesh Patel

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