I want to get clarification on the enabling/resetting the M4 because its not documented in the reference manual. From what I understand the following bits can cause the M4 to reset using the SCR (20D8000h) register
bit 3 - m4c_rst : M4 core reset
bit 4 - m4c_non_sclr_rst - Non-self-clearing SW reset for M4 core
bit 12 - m4p_rst : M4 platform reset
If the M4 isn't enabled from uboot via a bootaux, should it be possible to enable and reset the M4 (ie using bit 4 or bits 3+12) from a Linux application? From my testing with kernel 3.14:
1. enabling the M4 (bit 22) + resetting using bit 3+12 has no effect
2. enabling the M4 (bit 22) + resetting using bit 4 causes the kernel to hang.
As side note I would also like to point out the M4 is poorly documented as the reference manual no has description on what the M4 does when a reset occurs. From the code examples it seems to jump to address 0x007F8000 where it expects a Vector Table to exist?