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IMX6 EIM chip select address range partitioning

Question asked by Brian Busingye on Jul 6, 2015
Latest reply on Jul 6, 2015 by igorpadykov



Please clarify the following.


1) I would like to partition the EIM chip selects to 32M, is this done by setting IOMUXC_GPR1[1:2] = IOMUXC_GPR1[4:5] = IOMUXC_GPR1[7:8] = IOMUXC_GPR1[10:11] = 0


2) As specified on page 1955 of IMX6DQ Applications Processor Manual, if the address range of the four chip selects is set to 32M is the range below for each chip select correct

CS0: 0x8000000 -> 0x9FFFFFF

CS1: 0xA000000 -> 0xBFFFFFF

CS2: 0xC000000 -> 0xDFFFFFF

CS3: 0xE000000 -> 0xFFFFFFF