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K20 I2C: Why SDA Dips When Bus Direction Changes?

Question asked by Hui Shao on Jul 3, 2015

Hi-

 

We are using FB version of MQX I2C  driver (AN4652) to deal with sensors in device. We noticed that there is a dip happens when a received data has its MSB is 1, which can be seen in the captured picture below, where one byte is supposed to be read from slave device.

 

 

In the snapshot above, the first clock (upper row) is for the ACK sent from slave device. The dip happens right after it and before the first clock of data cycle. The data (0xFF) are about to be read out in next 9 clocks.

 

The interesting thing is, there is no such dip if the receiving data has its MSB as 0. The reason could be that the slave device is already holding SDA low and the dip is not visible.

 

Looking in the ISR inside driver code, the dip happens between the lines in red:

            else if (io_info_ptr->index == (io_info_ptr->index_repeat_start + 1))
            {
#ifdef DEBUG_ENABLE
               printf("change to r mode, %x \n", io_info_ptr->data[io_info_ptr->index]);
#endif
               _to_rx_mode(i2c_ptr);

               if (io_info_ptr->index == io_info_ptr->data_len)
               {
                  _give_nack(i2c_ptr);
               }
               else
               {
                  _give_ack(i2c_ptr);
               }

               // dummy read to start a reading operation
               io_info_ptr->data[io_info_ptr->index] = i2c_ptr->D;
            }

From the scope we know, when TX bit of C1 register is cleared for Rx, the SDA goes low (1st red line above). When TXAK bit of C1 register is set for NACK, SDA resumes to high (2nd red line above). In this case, a dip is generated. However, we don't see anything about changes the bit can cause bus transition from K20 user manual.

 

Although the SDA transition when SCL is low is OK in I2C specification, but we still want to know why bus direction turn-around can cause a dip on SDA line. Appreciated if someone could help.

 

Hui

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