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Scatter file modification to run large program on MQX (Cortex-M4 core)

Question asked by gurdeepak joshi on Jun 30, 2015
Latest reply on Jul 3, 2015 by alejandrolozano

Hello,

 

I am using Cosmic Phytec board running MQX on Cortex-M4 and using ARM-DS5 to generate binary file for MQX. I generated binary file for pingpong demo on m4 and its running fine, but when I try to run a large program (in same pingpong-m4 demo) on MQX running on Cortex-m4 core (Cosmic Phytec board), it shows following error at compile time:

 

Error: L6221E: Execution region DATA with Execution range [0x3f800000,0x3fbff56c) overlaps with Execution region KERNEL_DATA_END with Execution range [0x3f807fc0,0x3f807fd4).

 

- It appears that default scatter file needs to be modified. Please let us know what modification needs to be done.

 

Below are the contents of scatter file at  ../FSL-MQX/FreescaleMQXRTOS4.0.1/mqx/source/bsp/twrvf65gs10_m4/ds5/ram.scf

 

<code>

#! armcc -E

 

 

#define CODE_BASE_ADDR_START    0x3f000000

#define CODE_BASE_ADDR_END      0x3f03fff0

#define CODE_SIZE               (CODE_BASE_ADDR_END - CODE_BASE_ADDR_START)

 

 

#define DATA_BASE_ADDR_START    0x3f800000

#define DATA_BASE_ADDR_END      0x3f807ff0

#define DATA_SIZE               (DATA_BASE_ADDR_END - DATA_BASE_ADDR_START)

 

 

#define DATA_SHARED_START       0x3f040000

#define DATA_SHARED_END         0x3f04fff0

 

 

#define TCML_END                0x1f807ff0

 

 

;

; Note:

;   memory range 0x3f07ebf0 - 0x3f07eff0 is reserved for bootloader_vybrid segment

;

#define MY_ALIGN(address, alignment) ((address + (alignment-1)) AND ~(alignment-1))

 

 

 

 

LOAD_REGION_INTRAM CODE_BASE_ADDR_START

{

    VECTORS CODE_BASE_ADDR_START

    {

        vectors.o (.vectors_rom,+FIRST)

        vectors.o (.cfmconfig)

    }

   

    CODE +0

    {

        * (InRoot$$Sections)      ; All library sections for example, __main.o,

                                  ; __scatter*.o, __dc*.o, and * Region$$Table

        * (KERNEL)

        * (TEXT)

        * (+RO)

    }

   

    RAM_VECTORS DATA_BASE_ADDR_START ; For ram vector table. Used when  MQX_ROM_VECTORS is set to zero.

    {

        vectors.o (.vectors_ram)

    }

   

    DATA +0 ALIGN 32

    {

        * (+RW, +ZI)

    }

 

 

    KERNEL_DATA_START +0 ALIGN 16

    {

        * (KERNEL_DATA_START)     ; start of kernel data

        * (SRAM_POOL_START)

        * (UNCACHED_DATA_START)

    }

 

 

    KERNEL_DATA_END DATA_BASE_ADDR_END - (0x03*0x10)      ; RAM_END - 3 x aligned value with align 0x04

    {

        * (SRAM_POOL_END)

        * (UNCACHED_DATA_END)

        * (KERNEL_DATA_END)     ; end of kernel data

    }

 

    SHARED_RAM_START DATA_SHARED_START EMPTY 0xfff0

    {

    }

 

 

    SHARED_RAM_END DATA_SHARED_END

    {

        *(SHARED_RAM_END)

    }

   

    ; mem_init writes a storeblock_struct at the end of kernel data,

    ; max size 32 bytes, so use 0x100 offset

  

 

 

   BOOT_STACK_ADDR (TCML_END - 0x100) OVERLAY

    {

        *(BOOT_STACK)

    }

 

 

    ; We don't use their stack or heap, but the tools expect this

    ; to be here, so we have a dummy placeholder.

    ARM_LIB_STACKHEAP (TCML_END - 0x100) OVERLAY EMPTY UNINIT 0x04

    {

    }

}

 

</code>

 

 

Thanks,

Gurdeepak

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