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PMIC POR_B  Delay

Question asked by Katrina Gundal-Zaidi on Jun 25, 2015
Latest reply on Jun 25, 2015 by igorpadykov

How long after the PMIC POR_B is released from low to high does it take to read the config bits? Since we use a mux (FET switch) on these lines which are also used as the EIM interface to the FPGA we need to ensure we hold the enable signal to this low long enough.

 

I tried tying POR_B directly to the mux so it releases on the same edge as the i.MX6. (It says somewhere that these are sampled on the edge of por_B rising. It won’t boot in this case. This mux enable needs to be delayed for some amount of time and I need to know how long that is..

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