Unable to set Sabresd GPIO as output high

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Unable to set Sabresd GPIO as output high

3,041 Views
ASTRIHK
Contributor III

I'm using sabred imx6q and the platform is KK4.4.3_2.0.0 based on Linux version 3.10.53.

I tried to configure MX6QDL_PAD_EIM_D18__GPIO3_IO18 as output high during boot-up. No matter I used scope to measure the pin voltage or cat the file "sys/kernel/debug/gpio", the voltage is zero and gpio file showed "out lo".

What I modified the relevant files were shown as below.

In imx6qdl-sabresd.dtsi, I added

     test_ctrl {

        test-gpio = <&gpio3 18 0>;

    };

&iomuxc {

    pinctrl-names = "default";

    pinctrl-0 = <&pinctrl_hog_1>;

    hog {

        pinctrl_hog_1: hoggrp-1 {

            fsl,pins = <

                MX6QDL_PAD_GPIO_4__GPIO1_IO04   0x80000000

                MX6QDL_PAD_GPIO_5__GPIO1_IO05   0x80000000

                MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000

                MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000

                MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000

                MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000

                MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x80000000

                MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000

                MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x130b0

                MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000

                MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000

                MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000

                MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000

                MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000

                MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000

                MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000

                MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000

                MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x80000000

                MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000

                MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000

                MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0xc0000000

                MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000

                MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x80000000

                MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x80000000

                MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000

                MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000

                MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000

                MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000

                MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x80000000

                MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000

                MX6QDL_PAD_GPIO_1__WDOG2_B 0x80000000

                MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0

                MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x80000000 /*jackie*/

            >;

        };

    };

};

In mach-imx6q.c,

static void __init imx6q_test_init(void) /*jackie*/

{

    struct device_node *np = NULL;

    int ret, power_on_gpio;

    np = of_find_node_by_name(NULL, "test_ctrl");

    if (!np)

        return;

    power_on_gpio = of_get_named_gpio(np, "test-gpio", 0);

    if (gpio_is_valid(power_on_gpio)) {

        ret = gpio_request_one(power_on_gpio, GPIOF_OUT_INIT_HIGH,

            "test gpio On");

        pr_warn("!!request test On gpio********************\n");

        gpio_set_value(power_on_gpio, 1);

        if (ret)

            pr_warn("failed to request test On gpio**************\n");

    }

}

static void __init imx6q_init_machine(void)

{

    struct device *parent;

    mxc_arch_reset_init_dt();

    parent = imx_soc_device_init();

    if (parent == NULL)

        pr_warn("failed to initialize soc device\n");

    of_platform_populate(NULL, of_default_bus_match_table,

                    imx6q_auxdata_lookup, parent);

    imx6q_enet_init();

    imx_anatop_init();

    imx6_pm_init();

    imx6q_csi_mux_init();

    imx6q_mini_pcie_init();

   imx6q_test_init(); /* jackie */

}

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6 Replies

1,077 Views
igorpadykov
NXP Employee
NXP Employee

Hi Jackie

you can test this pad with memtool (read/write register) from imx-test package

and add debug printfs to codes printing gpio register value.

Index of /buildsources/i/imx-test/imx-test-3.10.53-1.1.0

Also one can try to use "gpio-leds" binding

https://www.kernel.org/doc/Documentation/devicetree/bindings/leds/leds-gpio.txt

[PATCH] ARM: dts: imx6qdl-sabreauto: Support debug LED — ARM, OMAP, Xscale Linux Kernel

Best regards

igor

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------

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1,079 Views
ASTRIHK
Contributor III

Hi igor,

Also, can I configure MX6QDL_PAD_EIM_D18__GPIO3_IO18 as output high in dtsi file directly rather than pin initialization in my imx6q_test_inti() api? If so, please kindly advise.

BR,

Jackie

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1,079 Views
igorpadykov
NXP Employee
NXP Employee
0 Kudos

1,079 Views
ASTRIHK
Contributor III

Hi Igor,

In imx6qdl-sabresd.dtsi, no matter what I set the default-state = "on" or "off", the output signal of MX6QDL_PAD_EIM_D18__GPIO3_IO18 is unchanged. What's wrong in this declaration?

leds {

        compatible = "gpio-leds";

        pinctrl-names = "default";

        pinctrl-0 = <&pinctrl_gpio_leds>;

        user {

            label = "debug";

            gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;

            default-state = "on";

        };

        /*charger-led {

            gpios = <&gpio1 2 0>;

            linux,default-trigger = "max8903-charger-charging";

            retain-state-suspended;

        };*/

    };

    pinctrl_gpio_leds: gpioledsgrp {

            fsl,pins = <

                MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x80000000

            >;

        };

BR,

Jackie

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1,079 Views
ASTRIHK
Contributor III

Hi igor,

When I replaced "MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x80000000" by "MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x4001b8b1", GPIO3_IO18 could be controlled to output high or low. Value 0x4001b8b1means to force the selected mux mode input path, I just wonder why I need to enable mux mode input path if GPIO3_IO18 is configured as output pin.

BR,

Jackie

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1,079 Views
ASTRIHK
Contributor III

Hi igor,

Value 0x4001b8b1means to force the selected mux mode input path, I just wonder why I need to enable mux mode input path if GPIO3_IO18 is configured as output pin

Can you also answer this question?

BR,

Jackie

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