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LVDS0 in U-Boot 2015.04 at imx6qSabreSD-based board.

Question asked by Ivan Nikolaenko on Jun 23, 2015
Latest reply on Jul 7, 2015 by Ivan Nikolaenko

Hi all!

 

I am trying to display SplashScreen logo at LVDS display in U-Boot. My mx6sabre_common.h configs is next:

/* Framebuffer */
#define CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
#define CONFIG_CFB_CONSOLE
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_IPUV3_CLK 260000000
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP

Now I can see crystal clear logo at the HDMI channel, but when I unplug HDMI and plug LVDS and reboot board I see my logo badly corrupted.

 

My LVDS display is interfaced over LVDS0 0-3 data lanes

LVDS0_TX0_N

LVDS0_TX0_P

LVDS0_TX1_N

LVDS0_TX1_P

LVDS0_TX2_N

LVDS0_TX2_P

LVDS0_TX3_N

LVDS0_TX3_P

 

Here are my LVDS-related code snippets:

static void enable_lvds(struct display_info_t const *dev)
{
    struct iomuxc *iomux = (struct iomuxc *)
                IOMUXC_BASE_ADDR;
    u32 reg = readl(&iomux->gpr[2]);
    reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
           IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT;
    writel(reg, &iomux->gpr[2]);
}

struct display_info_t const displays[] = {{
    .bus    = -1,
    .addr    = 0,
    .pixfmt    = IPU_PIX_FMT_RGB666,
    .detect    = NULL,
    .enable    = enable_lvds,
    .mode    = {
        .name           = "Hannstar-XGA",
        .refresh        = 60,
        .xres           = 1024,
        .yres           = 768,
        .pixclock       = 15385,
        .left_margin    = 220,
        .right_margin   = 40,
        .upper_margin   = 21,
        .lower_margin   = 7,
        .hsync_len      = 60,
        .vsync_len      = 10,
        .sync           = FB_SYNC_EXT,
        .vmode          = FB_VMODE_NONINTERLACED
} }, {
    .bus    = -1,
    .addr    = 0,
    .pixfmt    = IPU_PIX_FMT_RGB24,
    .detect    = detect_hdmi,
    .enable    = do_enable_hdmi,
    .mode    = {
        .name           = "HDMI",
        .refresh        = 60,
        .xres           = 1024,
        .yres           = 768,
        .pixclock       = 15385,
        .left_margin    = 220,
        .right_margin   = 40,
        .upper_margin   = 21,
        .lower_margin   = 7,
        .hsync_len      = 60,
        .vsync_len      = 10,
        .sync           = FB_SYNC_EXT,
        .vmode          = FB_VMODE_NONINTERLACED
} }};
static void setup_display(void)
{
    struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
    struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
    int reg;

    /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
    imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads));

    enable_ipu_clock();
    imx_setup_hdmi();

    /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
    reg = readl(&mxc_ccm->CCGR3);
    reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
    writel(reg, &mxc_ccm->CCGR3);

    /* set LDB0, LDB1 clk select to 011/011 */
    reg = readl(&mxc_ccm->cs2cdr);
    reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
         | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
    reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
          | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
    writel(reg, &mxc_ccm->cs2cdr);

    reg = readl(&mxc_ccm->cscmr2);
    reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
    writel(reg, &mxc_ccm->cscmr2);

    reg = readl(&mxc_ccm->chsccdr);
    reg |= (CHSCCDR_CLK_SEL_LDB_DI0
        << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
    reg |= (CHSCCDR_CLK_SEL_LDB_DI0
        << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
    writel(reg, &mxc_ccm->chsccdr);

    reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
         | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
         | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
         | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
         | IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT
         | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
         | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
         | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0
         | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED;
    writel(reg, &iomux->gpr[2]);

    reg = readl(&iomux->gpr[3]);
    reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
            | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
        | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
           << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
    writel(reg, &iomux->gpr[3]);
}

 

And another question: Is it possible to simultaneously display HDMI and LVDS0 at U-Boot?

I have not found answers to their questions on the forum.

 

Hope for your help!

 

Regards,

Ivan.

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