AnsweredAssumed Answered

SPI sck strange behavior

Question asked by PE TAPIE on Jun 22, 2015
Latest reply on Jul 6, 2015 by PE TAPIE

Hello Freescale community,

 

I use Kinetis Design studio 2.0.0, MQX KSDK 1.0.0 with Processor expert, (uc MK64F),

 

I realized SPI communication  using SPI0 and two channels DMA for Tx et Rx. I talk with a multiports (ADC,DAC, GPI,GPO) component at 4MHz.

 

I chose sck non-continuous for the configuration of the SPI

 

The frame format is 3 bytes : One for CMD, one for data LSB and one for data MSB.

 

I have a problem with reception of the first bit of each new byte because the sck signal has a strange behavior : the gap between two clock cycle is good but the gap between the 8th bit and the first bit of the next byte is different. You can see the behavior on the following screenshot :

 

SPI_Faults.png

 

with a zoom we can very well if the clock difference :

 

SPI_Faults_zoom.png

 

What the problem, Can you help me ?

 

I'am not interresting to use sck continuous mode,

 

I have found a solution for not having problem reading the first bit of new byte using functions :

 

static inline void DSPI_HAL_SetModifiedTimingFormatCmd(uint32_t baseAddr, bool enable)

and

static inline void DSPI_HAL_SetDatainSamplepointMode(uint32_t baseAddr,dspi_master_sample_point_t samplePnt) with "kDspiSckToSin_1Clock"

But signal MOSI is modify and I think this is not a properly operation

 

You can see with this modifications :

 

SPI_GOOD.png

 

Please can you give me some advices to resolve this problem ?

 

 

 

Outcomes