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K61 watchdog

Question asked by Lieven Schiltz on Jun 22, 2015
Latest reply on Jun 30, 2015 by Lieven Schiltz

Hi,

 

We use an MK61FX512VMJ15 with 150MHz core clock with ucLinux and are having some difficulty with the watchdog.

It is set to 5 seconds (LPO clock source). Most of the time, it works perfectly, but sometimes the board resets when initializing the watchdog module (after reboot, RCM_SRS0 indicates WDOG and WDOG_RSTCNT is incremented).

 

The driver code:

 

static void kinetis_wdt_unlock(void)
{
volatile int tmrout;

KINETIS_WDOG->unlock = KINETIS_WDOG_UNLOCK_KEY1;
KINETIS_WDOG->unlock = KINETIS_WDOG_UNLOCK_KEY2;

tmrout = ((KINETIS_WDOG->tmrouth << 16) | KINETIS_WDOG->tmroutl);
}

static void kinetis_wdt_start(void)
{
unsigned long flags;

raw_local_irq_save(flags);
/* Unlock configure & control */
kinetis_wdt_unlock();
/* Configure & control, must be within WCT window (]1, 250] bus cycles) of unlock */
/* Clear INT */
KINETIS_WDOG->stctrll = (KINETIS_WDOG_STCTRLL_INTFLG_MASK
     | KINETIS_WDOG_STCTRLL_RESERVED_MSK);
/* Configure */
KINETIS_WDOG->winh = 0;
KINETIS_WDOG->winl = 0;
KINETIS_WDOG->tovalh = (u16)(heartbeat >> 16);
KINETIS_WDOG->tovall = (u16)(heartbeat & 0xffff);
KINETIS_WDOG->presc = 0;
/* No test mode, dedicated clk (LPO 1kHz) */
KINETIS_WDOG->stctrlh = KINETIS_WDOG_STCTRLH_WAITEN_MSK
    | KINETIS_WDOG_STCTRLH_STOPEN_MSK
    | KINETIS_WDOG_STCTRLH_ALLOWUPDATE_MSK  /* Still allow updates */
    | KINETIS_WDOG_STCTRLH_RESERVED_MSK  /* Always keep at default (1) */
    | KINETIS_WDOG_STCTRLH_WDOGEN_MSK;  /* Start */
raw_local_irq_restore(flags);
}

 

We use a test script in a loop that:

start WDOG

kick WDOG every second, 5 times

stop WDOG

wait 10seconds

 

The reset caused by WDOG always happens when starting it. The loop can run anywhere between a few to a few hundred times before triggering the WDOG reset.

Note that:

- init is protected against interrupts so that unlock sequence and init code is executed in 1 block within WCT window

- added in kinetis_wdt_unlock() a read of tmrout to make sure that status & control registers only are accessed after at least 1 bus clock cycle after unlock as stated in K61 manual p612.

 

Can you see any reason why it still resets sometimes on init?

 

Best regards

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