DDR3 Calibration on i.MX53 with a 16-bit bus width failures

[compmas2]

I am attempting to perform the DDR3 calibration on an i.MX537 that is only using the lower 16 bits of the data bits.  I am unable to ever get back valid calibration results and instead all the tests return errors.  I have successfully configured the DCD before running the calibration so the memory bus is configured for 16bit access.

I am able to run DDR calibration on another i.MX537 based part that is using the full 32-bits of the data bits and is also using the same DDR3 chip and general layout.  The one main exception is there is a single DDR3 chip connected to the lower 16 data bits instead of two chips, each using 16 data bits for a total of 32 data bits.

Is the i.MX53 just not able to perform DDR calibration when only 16 data bits are used?

[Yuri]

  From SOC design team : “i.mx53 doesn't support 16 bits HW auto
calibration. SW calibration is needed." Please refer to app
note AN4466 regarding calibration details.

Have a great day,
Yuri

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[compmas2]

Are there any existing tools already made that run the SW calibration or will I have to write my own?

[Yuri]

  Sorry - no. We do not have examples, except described in the AN4466.

Regards,

Yuri.