We are planning to interface 2 CSI camera modules each with 2 data lanes to i.MX6Q processor (Camera#1:Dat0 and Dat1, Camera#2 :Dat2 and Dat3) and share the CSI lane Clock for both.
We will not use both the Camera's simultaneously.
Can we configure CSI data lanes Dat2 and Dat3 as lanes Dat0 and Dat1 respectively for the Camera#2? We plan to reuse the same Camera module as Camera#1 for Camera#2.
Is there any way we can inform the processor about this lane allocation?