Cannot set a frequency of 29.5 MHz for the LVDS clock signal on Yocto and LTIB

[charleshuang]

When I set a frequency of 29.5 MHz for the PLL2 LVDS clock signal, I measure the value is always 38 MHz by oscilloscope.

1. I refer to the following URL, is it a feasible solution for Yocto 3.10.17.1.0.2?

    When other peripheral equipments reference to this LVDS clock, will they be affected?

    Reference URL: https://community.freescale.com/thread/306801

2. How to solve this issue for LTIB 4.1.0?

Thank you.

Best Regards,

Alex

[gusarambula]

Hello Charles Huang,

Yes, you may apply the recommended solution on the thread mentioned.

Please keep in mind that the clock configuration may not allow for all desired values to be reached. You may open a SR to ask for an i.MX6 Clock Configuration that may be of help in order to see more graphically how clock dependencies are met.

I would recommend using Yocto if possible as current BSP releases and the community BSP are based in Yocto and LTIB hasn’t been updated in a while and may be a bit more buggy.