When I set a frequency of 29.5 MHz for the PLL2 LVDS clock signal, I measure the value is always 38 MHz by oscilloscope.
1. I refer to the following URL, is it a feasible solution for Yocto 18.104.22.168.0.2?
When other peripheral equipments reference to this LVDS clock, will they be affected?
Reference URL: https://community.freescale.com/thread/306801
2. How to solve this issue for LTIB 4.1.0?