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KL02Z inconsistent SWD response

Question asked by Haim F on Jun 16, 2015
Latest reply on Jul 7, 2015 by Haim F

Hi,

I'm hoping for some guidance in regards to using SWD to access the FRDM-KL02Z board.

I connected 2 GPIO pins on my board to the SWDIO and SWDCLK pins on the board for SWD access to the FRDM-KL02Z board.

I was using the instructions on this forum discussion

https://community.freescale.com/thread/350691

to configure the SWD initialization sequence, and I was able to read the IDCODE and get access to the access port.

The problem I encounter is inconsistency in the board response. I am able to recreate it as follows:

Initialization sequence:

  • SWDCLK is set to output.
  • Host turns SWDIO into an output and drives it high, SWDCLK is strobed from high to low 64 times.
  • 0x9E is sent LSb First over SWDIO by the host
  • 0xE7 is sent LSb First over SWDIO by the host
  • Host turns SWDIO into an output and drives it high, SWDCLK is again strobed from high to low 64 times
  • SWDIO is set low and the clock is strobed once
  • Header to read IDCODE is formed and sent, ACK OK received, 32 bits of Data recieved, 1 parity bit received, Data is 0x0BC11477

I then, try to redo the last action- read the IDCODE many times.

After several retries (the amount of retries is inconsistent) of successful reads, I get a fault ACK- which can be 0x4 or 0x7 (which are illegal ACKs in debug port accesses), and I have to redo the init sequence in order to be able to read again.

This problem happens in all kind of read/write operations to the debug and the access ports. I used scope to get the signals coming from the board, and I see that the ACK signals are indeed faulty.

Do you have any idea, what might cause this inconsistency in the board’s response?

 

Many thanks,
Haim

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