Currently working on implementing hardware gpio trigger support in Linux using the IIO subsystem for the Vybrid ADC driver. Have got a working implementation ready, but, there are few things which are currently not clear to me on reading the Vybrid TRM when it comes to using multiple channels and my trial and error approach has not cleared my understanding.
Trigger support for ADC requires configuration of the Programmable Delay Block peripheral. In the PDB block, there is a Channel n Control Register 1 in which there is the Pre Trigger output select and Pre trigger enable bit fields. There are two valid bit fields, however there configuration is currently not clear to me.
Is it possible to configure the PDB block for triggering and allow sampling of multiple channels? From the Page 1747 of the TRM which describes the register and the corresponding functional description on 1750, this would seem possible, however trying to configure the PDB currently gives me sequencing errors. The operations I currently perform are as follows
1. Set the bit 0 and 1 of the TOS and EN field of CH0C1 register
2. Set ADC_HC0 to one channel from ADC0 and ADC_HC1 to another channel from ADC0. For my case this is channel 8 and 9 with the ADC0 block.
3. Set a delay with the CH0DLY0 and CH0DLY1 registers.
4. Finally set PDBEIE, PDBEN and LDOK
This immediately raised the PDB sequencing error interrupt handler which I have configured when the hardware trigger is given with the GPIO. So my configuration seems wrong. What is the correct way to configure the PDB for multiple channels? From what I understand atleast two simultaneous channel readings should be possible and from what I read on two other posts which I found in the community, it should be doable?
Can someone clarify the PDB configuration to me for the above use case?
Also the so called back to back operation description does not help much, nor the one given on Page 1747 or the diagram on Page 146 of the TRM. Can someone shed some light on this as well?
Thanks & Regards,