What are the requirements/ramifications of running the eLBC at 2.5V?

[toddreed]

I see that we have to connect BVDD to 2.5V, which will make GPIOs 8-15 2.5V as well.  Are there any more issues?  The FPGA we are using has some 2.5V max banks that we need to utilize, so running the eLBC at 2.5V would save some pins.  Most of the rest of the board runs at 3.3V.

[LPP]

What part are you asking about? For distinctness, i will reply about P2041.

P2014 supports BVDD 3.3/2.5/1.8 V.

Processor provides the I/O voltage select inputs IO_VSEL[0:4] to configure the receivers and drivers of the I/Os associated with the BVDD, CVDD, and LVDD power planes. Incorrect voltage select settings can lead to irreversible device damage.

Actual settings are shown in P2041EC Section 3.2 "Supply Power Default Setting of P2041EC".

No other issues.

Have a great day,
Pavel

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[toddreed]

Hi Pavel,

Thanks for your quick response!

We are using the P2020 and I don't think there are any IO_VSEL lines.  So, just connecting BVDD to a selected voltage and making sure the associated pins are connected to devices of the same voltage?

Thanks again,

Todd

[LPP]

Please refer to P2020RM Section 4.5.4 Voltage selection configuration

"For proper use, the voltage select device input signals LVDD_SEL, BVDD_VSEL[0:1],

and CVDD_VSEL[0:1] must be statically tied to reflect the voltage applied on the

LVDD, BVDD, and CVDD I/O supplies respectively...

As an example, for local bus operation at 2.5 V, the BVDD_VSEL[0] and

BVDD_VSEL[1] device inputs must be configured to 01 and thus be tied on the board to

GND and OVDD respectively. For 2.5 V operation, tying BVDD_VSEL[0] and

BVDD_VSEL[1] to anything except GND and OVDD respectively can lead to

irreversible device damage."

Have a great day,
Pavel

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