imx6 adv7180 video capture

[angelo_d]

Dear Gentlemen,

i have imx6q board with adv7180 mounted with same schematic of sabreauto. With one exception: input is Y-C (Ain1 and Ain4).

I work with kernel 3.10.17.

So, used same adv7180 devicetree as in sabreauto, but adapting the driver to use Y-C input (just set adv7180 input mask as 0110).

Capturing, using a composite to Y-C adapter, i have this error:

MFW_GST_V4LSRC_PLUGIN 3.0.11 build on Apr 29 2015 10:07:23.

mxc_v4l_open: Mxc Camera no sensor ipu0/csi1

MFW_GST_V4LSINK_PLUGIN 3.0.11 build on Apr 29 2015 10:07:19.

Setting pipeline to PAUSED ...

/GstPipeline:pipeline0/MFWGstV4LSrc:mfwgstv4lsrc0.GstPad:src: caps = video/x-raw-yuv, format=(fourcc)I420, width=(int)720, height=(int)576, framerate=(fraction)30/1, pixel-aspect-ratio=(fraction)1/1

Pipeline is live and does not need PREROLL ...

Setting pipeline to PLAYING ...

New clock: GstSystemClock

ERROR: v4l2 capture: mxc_v4l_dqueue timeout enc_counter 0

ERROR: from element /GstPipeline:pipeline0/MFWGstV4LSrc:mfwgstv4lsrc0: Internal data flow error.

Additional debug info:

gstbasesrc.c(2625): gst_base_src_loop (): /GstPipeline:pipeline0/MFWGstV4LSrc:mfwgstv4lsrc0:

streaming task paused, reason error (-5)

Execution ended after 9999460335 ns.

Setting pipeline to PAUSED ...

Setting pipeline to READY ...

/GstPipeline:pipeline0/MFWGstV4LSrc:mfwgstv4lsrc0.GstPad:src: caps = NULL

Setting pipeline to NULL ...

Total rendered:0

Freeing pipeline ...

[--->FINALIZE v4l_sink

bash-3.2# power_down_callback: ipu0/csi0

I already searched the forum for "ERROR: v4l2 capture: mxc_v4l_dqueue timeout enc_counter 0" without any useful result.

I am capturing a small 9'' TV output converted from composite to Y-C, and also from a small camera.

I add some more info:

I see clock correctly generated while capturing (on ADV7081 ext crystal pins)

I see Y-C signals correctly arriving on ADV7081 Ain1 and Ain4

I don't see any data bit ouput on DA4/19 while capturing.

Every help is appreciated. Thanks

[alejandrolozan1]

Hi,

I just checked L3.10.53 and I found this code ( drivers/media/platform/mxc/capture/adv7180.c):

	if (cvbs) {
	/* Set CVBS input on AIN1 */
	adv7180_write_reg(ADV7180_INPUT_CTL, 0x00);
	} else {
	/*
	* Set YPbPr input on AIN1,4,5 and normal
	* operations(autodection of all stds).
	*/
	adv7180_write_reg(ADV7180_INPUT_CTL, 0x09);
	}

It seems that if cvbs property is not found in the devicetree the other configuraiton is

1001 YPrPb Y input on AIN1, Pb input on AIN4, Pr input on AIN5

I would try to modify the code in the next way:

	if (cvbs) {
	/* Set CVBS input on AIN1 */
	adv7180_write_reg(ADV7180_INPUT_CTL, 0x00);
	} else {
	/*
	* Set YPbPr input on AIN1,4,5 and normal
	* operations(autodection of all stds).
	*/
	adv7180_write_reg(ADV7180_INPUT_CTL, 0x06);
	}

And remove the cvbs property in de devicetree.

Please try that and let me know how it goes.

/Alejandro

[angelo_d]

Hi alejandrolozano ,

many thanks for the help.

I already modified that driver part for Y-C, adding a "2" value from device tree, and setting "0110".

But to avoid any issue, i am now working with cvbs, so "0000" and cvbs set to "1".

Even with poor signal, since i see the synch signals in output, i was expecting some garbage as output, so at least some bit.

But no data is visible in the output bus D0-D15.

Linux correctly times out, becouse it expects the EOF bt656 pattern that is not arriving.

I suspect on the reset sequence. Or in a bad init due to some i2c bus issue.

Regards

[alejandrolozan1]

Hi,

Yes, I agree that it must be some other configuration missing. Unfortunately I am not an expert of this field but after checking the documentation I found this:

"Mandatory write required for Y/C (S-Video mode) Reg 0x58 = 0x04; see Reg 0x58 for bit description."

Our code configures that register to 0x00;

adv7180_write_reg(0x58, 0x00);

It's worth trying to change that register and test it.

Best Regards,

Alejandro

[angelo_d]

Hi alejandro,

well, i already tried, but no way. I am now working with composite signal so i suppose the driver as is should give some image.

I see capturing (linux gstreamer command) the chip start to produce clocks and synchs, but is not clear to me how this begin, since i don't see any i2c command.

[angelo_d]

some updates,

capturing with

gst-launch mfw_v4lsrc ! mfw_v4lsink

before the error, for some seconds, i get:

VSYNC, HSYNC, FIELD and PIXOUT correctly out from the chip, but nothing in the data lines.

[angelo_d]

Hello,

still nothing good, some more info:

Capturing from a small camera 720x576 PAL/NTSC, singnal on composite input, i measure:

XTAL 28,571Mhz

HS 16,129 Hz

VS 60,24 Hz

Pixclk 27 Mhz

Nothing in data lines. v4l2 driver times out for some reason, with 0 bytes read.

Enabling GST debug i get

New clock: GstSystemClock

ERROR: v4l2 capture: mxc_v4l_dqueue timeout enc_counter 0

0:00:11.319484002   740  0x15ec0c0 ERROR             mfw_v4lsrc mfw_gst_v4lsrc.c:1250:mfw_gst_v4lsrc_buffer_new: >>V4L_SRC: VIDIOC_DQBUF failed.

Every help is appreciated. Thanks