MPC5777C ADC conversion time

[s_dileep27]

Hi,

Greetings!!

Through external triggering method, I am trying to get the fastest possible conversion rate in eQADC module. (with DMA enabled)

Here is the brief explanation on bit low level -

--> CFIFO 1 is used and the trigger method is by PIT timer interrupt.

--> Clock input to ADC is 80Mhz(non-fm peripheral freq after the sysdiv)/ 4(PS setting) = 4Mhz ........... As per reference manual, 24Mhz is max freq of ADC operates so factor 3 is not advised to use - Correct me if I am wrong.

--> DMA ch2 & 3 enabled to push and pop ...... Round robin method is implemented. (fm peripheral input frequency is 120Mhz)

--> 4 channels need to be converted simultaneously

--> 12 bit, 2 sample rate, 2 count clocks

With my implementation, I achieved 5.7 micro seconds as least possible conversion rate-- (Implemented a GPIO's toggling logic in PIT & DMA ISR's to check this)

Now my questions is - how far I can improve this response

My requirement is to make the total conversion time as low as possible.
Please suggest more configuration changes that need to be done to achieve my requirement.

Also If I give same signal to two channels of ADC and trigger, I should get the same counts--- Indirectly I want to get exact response at exact instant of trigger.

Tried using both ADC0 & ADC1 enabling but couldnt get. Fed a same sine (0-5V) wave to two different channel but the counts measured are differing by 40 - 50

This is same case with using ADC0 alone.

I mean to say there is not much difference in response by using Single ADC0 & both ADC's. There is no improvement in total conversion time and also the response.

One info is.. when I use more channels for conversion there is some improvement in conversion time.

Please help regarding this

thanks in advance
- Dileep

[davidtosenovjan]

Maximum fADCLK is declared as 33MHz although it is not yet characterized. Minimum number of ADC clocks required is 16 (considering single ended conversion). It gives 2Msps per converter thus 4Msps total.

Fastest rate you achieve by using of continuous scan with DMA command filling and result draining. But this DMA triggering must be initated by eQADC module (by CFFFx and RFDFx flag) so DMA channel sources 0-11 must be used for this purpose. PIT are not supposed to be involved it that anyhow.