Sven Habermann

External interrupt (INT) at HC12

Discussion created by Sven Habermann on Nov 27, 2007
Latest reply on Sep 26, 2008 by David Kelly
Hi @all,

I have a question regarding the handling of (external) interrupts (e.g. IRQ) if the (maskable) interrupts are localy enabled (e.g. IRQCR) and globaly disabled via the I-bit in CCR.

As far as I understand an occuring interrupt will pend until the global interrupts enabled again via the I-bit in CCR. Is that correct?

For the external interrupt (IRQ) no "flag" is implemented. Thus I'm not sure what happen if the external interrupt (IRQ) occurs while global interrupt disabled. So if the IRQ is configured as edge-sensitive the edge-detecting latch will most likely cause also a pending interrupt that will be handeled after the global interrupt enabled again. Is that right? What happens with an level-sensitive interrupt that occurs and disappears (IRQ goes low and high again) while global interrupts disabled? The interrupt is also pending or will it be lost?

Thanks in advance,
Sven

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