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I2C loop back test in iMX6 CPU

Question asked by Mohammed Azlum on Jun 4, 2015
Latest reply on Jun 4, 2015 by Mohammed Azlum

Hello FSL,

 

Is it possible to do the I2C1 & I2C2 loop back test in same iMX6 processor ?

 

Example,

Time T1

I2C1 is act as master and I2C2 is act as slave at time T1. So that master and slave can be communicated (example send and receive data) in same processor. Thus we can make sure that I2C1 master & I2C2 slave functionalities are working properly. 

 

Time T2

Similar way,

I2C1 is act as slave and I2C2 is act as master at time T2. So that master and slave can be communicated (example send and receive data) in same processor. Thus we can make sure that I2C1 slave & I2C2 master functionalities are working properly. 

 

Also here I have atathced the wiring diagram of the I2C loop back test. Could you review and share the feedback ?

I2C1 & I2C2 Loop Test.png

 

Regards,

Azlum

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