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Long ~30uS delay between SPI byte transmissions in fsl_dspi during call to DSPI_DRV_MasterTransferBlocking(), what causes it?

Question asked by Chad Williams on Jun 3, 2015
Latest reply on Jun 21, 2015 by Chad Williams

I have been testing an application that writes to an LCD using SPI and have noticed its slow and decided to look into the cause.

 

Processor MK24FN1M0120VLL

CPU clock 20.97152MHz

SPI clock rate  2.097MHz

SPI intance   DSPI2  ( 1 byte FIFO)

KSDK version 1.2.0 using Processor expert for driver configuration, KDS3.0

 

 

the display data is being written in successive calls to :

dspiResult = DSPI_DRV_MasterTransferBlocking(FSL_DSPICOM1,NULL, pagebuf,NULL, bufindex+1, LCD_MASTER_TRANSFER_TIMEOUT);

 

close inspection of the data being transmitted revealed there is about 32 microseconds delay between each byte

and each byte takes 3.8 microseconds  to transmit.  I want to significantly reduce this 32 uS delay in order to make display refresh activity  not visible to the user.

 

I have done some digging and found there are programmable delays  and have made a call to adjust the delay after transfer to 476nS

status = DSPI_DRV_MasterSetDelay(instance, kDspiAfterTransfer, 476, & calculatedDelayaftertransfer);

if (status != kStatus_DSPI_Success) return;

 

but this code returns with kStatus_DSPI_Success but appears to have no effect.

 

Since its a simple blocking write to SPI from a buffer, the code should write to SPI without significant delays.

Is there anything I should do to eliminate the delay between bytes?

 

I have attached an image of the master configuration in PE

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