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IMX6 DDR3 Stress test and DRAM layout

Question asked by James CHUNG on Jun 3, 2015
Latest reply on Jun 5, 2015 by James CHUNG



We modified Sabresd board, but DDR Stress test was passed at 475MHz.

At 500MHz or 528MHz, writing level calibration seems odd and boards were failed at 500MHz or 525MHz.

Currently we are using IMX6D (dual core).


See below.

MMDC_MPWLDECTRL0 ch0 after write level cal: 0x0013000F

MMDC_MPWLDECTRL1 ch0 after write level cal: 0x00150013

MMDC_MPWLDECTRL0 ch1 after write level cal: 0x00040013

MMDC_MPWLDECTRL1 ch1 after write level cal: 0x017F000A


In 475MHz,  MMDC_MPWLDECTRL1 ch1 was 0x0001000B, but it changed to 0x017F000A.


We are planning to revise board soon. Do you have any idea to resolve this matter and achieve 528MHz or higher?

Is there any restriction on number of vias?

Or, variation of length of trace?


Thanks in advance.