I am writing a bare metal NOR flash driver for the T1040RDB board.
I planned to use IFC page read mode (IFC_CSORn_NOR.PGRD_EN = 1) in order to speed up data reading through DMA, but once activated, I observe a few errors when reading single data.
The problem comes while controlling erasing operation: after launching the erase sector operation, I have to read words at any flash address (but always at the same address), until a specific status bit stop toggling, signaling end of erasing.
A typical toggling sequence is: 0x48 0x08 0x48 0x08 0x48 0x08…
When error occurs, the sequence is e.g.: 0x48 0x08 0x48 0x48 0x08 0x48…
Thus it seems that sometimes (approx. once every 20000 read), when 2 single read accesses are made consecutively, there is only one effective bus transaction, so the same value is reported twice to core bus.
Is it a known behavior? Can it be another problem?
For PGRD_EN = 1, RM says: Software should issue transaction based on device page size
So I wonder if it is a mandatory requirement? (should “should” be “must”?)
For information, the flash is accessed with a cache-inhibited and guarded TLB, and I use volatile data pointer.
Thanks for any information!