i try to adjust several register of CCM like CSCMR1, CSCDR3 for ajust IPU1_HSP and MIPI_PIXEL clocks.
I try to get HSP > MIPI_PIXEL > 225 MHz
hsp_clk > ccm_pixel_clk/0.9 > (mipi_clk_lane frequency /(8bits*2))*Data_lane_number
in my case clock lane = 999MHz with 4 lanes.
I see all clock definition in arch/arm/mach-imx/clk-imx6q.c but if the clock lane change it is useful to cahnge clock settings in my driver.
What is the process to set a new rate inside a driver ?
and why when i change the clok lane on mipi csi bus in the mipi_info structur does'nt change ?
thanks for your suggestion.