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S12G48 ECC Logic Test pattern for 2 bits error simulation

Question asked by Sorin Stan on May 29, 2015
Latest reply on Jul 17, 2015 by Radek Sestak

Hello

 

We currently have the following technical issue:

 

Processor: S12G48

 

Problematic: according to Safety Considerations S12G-Family Rev.0 7/2012 , Chapter 6.1 Program Flash and EEPROM, in "ECC Logic not working" paragraph, it is stated that the ECC Logic may be tested by programming a carefully choosen pattern combination. In the same paragraph we have an example of "producing" an 1 bit error. For our application we need a pattern example that covers the case of the 2 bits errors. The purpose is to test the ECC Logic during application startup with a controlled uncorrectable 2 bits error. By reading the respectively prepared pattern, we would determin if the detection of the 2 bits errors is working properly before continue execution.

 

Question: Is anybody able to provide such pattern combination to generate a 2 bit error in the Program Flash?

 

Many thanks

Sorin

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