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About QSPI clock setting .

Question asked by Takashi Takahashi on May 28, 2015
Latest reply on Jun 17, 2015 by alejandrolozano

Hi community.


I refered VYBRIDRSERIESEC_Rev_7.pdf of p58"9.5.1 QuadSPI timing".

The QSPI_MCR [DDR_EN] a set (to 1b)in the state, if sent  the command Programing of "SDR", then

I am recognized as to the operation of p59 of "QuadSPI Output / Write timing (SDR mode)" .


whether I should refer to either the operating conditions of this case,

Of p59 "QuadSPI Output / Write timing (SDR mode)" or of p61 "QuadSPI Output / Write timing (DDR mode)"

Whitch referred to either of?

In operatively "SDR mode", SCK  is within the range in the current setting of 69.88MHz in MAX80MHz,
However, when referring to "DDR mode", since the MAX has a 45MHz, it will over the upper limit.

Please teach me SCK setting is no problem at 69.88MHz.

And would you please replay of previous question of ( I want to calculate  of  ”Read freaquency calculations", "Max read frequency", "Hold timing").