I am design new project schematic by using P2040 and micron ddr3.
one DDR3 spec is 2Gb, 16bits, MICRON DDR3 part number is MT41J128M16JT-125.
and I find the P2020 reference design schematic. why the data bus lines are irregular and cross between p2020 and ddr2.
for example, DDR2_DQ13--->DQ0, DDR2_DQ14--->DQ1, DDR2_DQ8--->DQ2. etc.
I upload the reference schematic. please help me to analysis it.
Additionally, if you have the correct reference design shematic about p2040 and ddr3, please send it to me.