If using MPC5748G.h revision 1, address of the mentioned register is 0xFFFF 08A0.
If using MPC5748G.h revision 3, address of the mentioned register is 0xFFFF 01C0. This is the address, specified in the actual RM (MPC5748G Reference Manual, Rev. 3 , 04/2014)
According to the statement here: Re: MPC5748G: What is the purpose of PLLDIG.PLLCAL3 register (not present in MPC5748GRM) and how to configure it? up to date revision of header file is revision 3, where address corresponds to the actual RM.
When I'm using MPC5748G.h revision 3 and trying to run PLL from the "Fast external crystal osc. (FXOSC)", MCU stays at "Fast Internal crystal osc. (FIRC)" clock, i.e. I'm unable to use FXOSC.
When I'm using MPC5748G.h revision 1, clock is changed from FIRC to FXOSC.