We want to synchronize the LVDS output with external CLK and VSYNC.
We have some questions.
We think that the LVDS output can be synchronized by external CLK and VSYNC.
Is our understanding right?
2) In Figure 37-39. DI's block diagram(P.2855), EXT_CLK and EXT_VSYNC are listed.
However, these signals are not listed in Table 37-6. IPU1 External Signals(P.2747-).
Which pin should these signals be input into each?
May I have advice?