P4080: How to support 4GB DDR3 in Linux kernel?

amitshah1 · ‎05-24-2015

Hi All,

I'm working on P4080 based system with Linux running on it. It has 4GB ddr3 memory(2GB per controller).

During boot-up, kernel is crashing if i don't mention the size in bootargs, and kernel is booting-up when i passed only 2GB ddr3 size in u-boot bootargs which actually has 4GB ddr3 memory. I've enabled 4GB(2GB per ddr3 controller) in u-boot with using 36-bit physical addressing.

Also in u-boot bootup , it says 2GB left unmapped, which later on came to know that P4080 platform specific ddr initialization is using max 2GB size.

I've enabled "large physical address support" and SWIOTLB options in kernel also, still giving same error. Device tree file also using 36-bit physical addressing.

Is there anything still we have to enable to use 4GB memory in Linux? Please share your ideas guys..

Kernel crash comes as:

===================================================================================

Machine check in kernel mode.

Caused by (from MCSR=8000): Load Error Report

Oops: Machine check, sig: 7 [#1]

SMP NR_CPUS=8 CoreNet Generic

Modules linked in:

CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.12.19-rt30-QorIQ-SDK-V1.6+gc29fe1a #23

task: ee084a30 ti: efbae000 task.ti: ee0a2000

NIP: c01ef070 LR: c01ef060 CTR: 00000000

REGS: efbaff10 TRAP: 0204 Not tainted (3.12.19-rt30-QorIQ-SDK-V1.6+gc29fe1a)

MSR: 00029002 <CE,EE,ME> CR: 84844e48 XER: 00000000

GPR00: c01ef01c ee0a3c30 ee084a30 f1049040 c0325214 c03b9ec4 ee1d2ba0 00000fe4

GPR08: 38241215 00000000 f104a278 38241215 84844e88 00000000 c00027f0 00000000

GPR16: 00000000 20000000 00000000 c039222c 00500001 ed010d20 00000002 c02a230c

GPR24: c03b1044 c02a21f0 c0389fb8 ee2810c0 00000000 ee1d6400 00000000 f1048000

NIP [c01ef070] n_tty_open+0x70/0x130

LR [c01ef060] n_tty_open+0x60/0x130

Call Trace:

[ee0a3c30] [c01ef01c] n_tty_open+0x1c/0x130 (unreliable)

[ee0a3c50] [c01f3c1c] tty_ldisc_open.isra.6+0x5c/0xa0

[ee0a3c60] [c01f4544] tty_ldisc_setup+0x24/0xc0

[ee0a3c80] [c01eb698] tty_init_dev+0xb8/0x1e0

[ee0a3ca0] [c01ec3b0] tty_open+0x330/0x680

[ee0a3d00] [c00eaedc] chrdev_open+0xbc/0x1c0

[ee0a3d30] [c00e3dc0] do_dentry_open.isra.15+0x190/0x2b0

[ee0a3d50] [c00e3f0c] finish_open+0x2c/0x60

[ee0a3d60] [c00f504c] do_last.isra.47+0x3fc/0xbe0

[ee0a3dd0] [c00f58e4] path_openat+0xb4/0x640

[ee0a3e30] [c00f6cb0] do_filp_open+0x30/0x90

[ee0a3eb0] [c00e52f8] do_sys_open+0x148/0x280

[ee0a3ef0] [c03558fc] kernel_init_freeable+0x160/0x1d0

[ee0a3f20] [c0002808] kernel_init+0x18/0x170

[ee0a3f40] [c000fca4] ret_from_kernel_thread+0x5c/0x64

Instruction dump:

913f0034 388451f8 4be8e5a9 3c80c032 387f2270 7fc5f378 38845214 4be8e595

93fd01a0 3bc00000 93df2244 387f1040 <893f003d> 38800000 93df0004 38a00200

---[ end trace 91dd2f21b34be299 ]---

Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000007

Rebooting in 180 seconds.

===================================================================================

Regards,

Amit Shah

yipingwang · ‎05-29-2015

Hello AMIT SHAH,

Please download QCVS Tool from CodeWarriorNetworked Applications : QCVS|Freescale, and use it to generate DDR configuration for your 4G DDR, then use DDRv Tool to do further adjustment.

Have a great day,
Yiping

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yipingwang · ‎05-27-2015

Hello AMIT SHAH,

For P4080, by default 36 bit mode is supported(u-boot, Kernel) in Linux SDK.

Please check whether your problem is caused by MMU TLB definition.

TLB definition is invoked in board/freescale/corenet_ds/ddr.c, the function setup_ddr_tlbs is defined in

arch/powerpc/cpu/mpc85xx/tlb.c.

Please refer to the following code

unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr,

unsigned int memsize_in_meg)

{

unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;

u64 memsize = (u64)memsize_in_meg << 20;

memsize = min(memsize, CONFIG_MAX_MEM_MAPPED);

memsize = tlb_map_range(ram_tlb_address, p_addr, memsize, TLB_MAP_RAM);

if (memsize)

print_size(memsize, " left unmapped\n");

return memsize_in_meg;

}

The variable CONFIG_MAX_MEM_MAPPED is defined in ./arch/powerpc/include/asm/config.h.

#ifndef CONFIG_MAX_MEM_MAPPED

#if defined(CONFIG_4xx) || \

defined(CONFIG_E500) || \

defined(CONFIG_MPC86xx) || \

defined(CONFIG_E300)

#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)

#else

#define CONFIG_MAX_MEM_MAPPED (256 << 20)

#endif

In the configuration file include/configs/corenet_ds.h, DDR size has already been assigned to 4G.

So please enlarge CONFIG_MAX_MEM_MAPPED to 4G.

Have a great day,
Yiping

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scottwood · ‎05-27-2015

Please do not follow this advice. It is wrong and will probably result in a non-booting U-Boot due to conflicting TLB entries between DDR and I/O. As I said in my other reply, this U-Boot limitation has nothing to do with Linux being able to access the full 4 GiB.

amitshah1 · ‎05-27-2015

Hi,

Yes, when i tested making CONFIG_MAX_MEM_MAPPED to 4G in .h file, it got stocked in ddr stage and not able to boot.

As Scott sugested, i'm trying to debug with ddr configuration settings. And yes some time i got following message in uboot,

==================================================

DRAM: Initializing....using fixed parameters

Configuring DDR for 1300 MT/s data rate

Waiting for D_INIT timeout. Memory may not work.

2 GiB left unmapped

4 GiB (DDR3, 64-bit, CL=9, ECC off)

Testing 0x00000000 - 0x7fffffff

Testing 0x80000000 - 0xffffffff

Remap DDR 2 GiB left unmapped

POST memory PASSED

==================================================

But the thing is, when i'm testing with Lauterbach debugger and ddr config file generated with codewarrior tool, each 2G memory associated with each ddr3 controller is getting properly initialized and read/write test was passing.

And same configuration i'd added in uboot ddr init routine. Anyway i'll again debug ddr settings and post here.

Is there possiblity that ddr will work if i lower ddr operating frequency?

Thanks,

Amit

scottwood · ‎05-28-2015

Memory tests often miss issues that arise during real usage, and CodeWarrior may not know about aspects of the board design that influence the required timing. I'm not an expert in DDR timings, but from what I've seen, there's a certain amount of experimentation done to find the right timings for a given board.

scottwood · ‎05-26-2015

You don't have to do anything special to support 4GiB RAM. The U-Boot message about leaving 2GiB unmapped is only about the TLB mappings U-Boot uses and has nothing to do with how Linux accesses DDR.

The machine check indicates a problem that you need to address. Maybe there's a bad DDR chip above 2GiB -- does this happen on more than one board? Maybe the DDR timings are wrong, or the board has a problem with signal integrity on the connection to the second DDR controller, etc. It's not a Linux problem.