AnsweredAssumed Answered

Which register controls i.MX6Q "USB_OTG_PWR" external signal?

Question asked by Miles Wang on May 22, 2015
Latest reply on May 25, 2015 by igorpadykov

Dear sir,


There is an external signal "USB_OTG_PWR" in i.MX6Q processor. I want to know which register (which bit) control its output.

If set the bit, the OTG_VBUS is powered on. Otherwise OTG_VBUS is powered off.

In i.MX6Q SD board, the signal is "USB_OTG_PWR_EN". I want control OTG_VBUS on/off by software.

PP (bit 12) of USBC_n_PORTSC1 seems not work (always powered on) in i.MX6Q SD board. Is there anything else?

Background: We have implemented the low power mode (ARM core power down and DDR in self-refresh) in i.MX6Q SD board.

But after exiting from low power mode, u-disk can't be accessed any more. u-disk always responses STALL.

After remove u-disk and insert it again, u-disk works again.

So the workaround is to simulate the removal/insertion action of U-disk after exiting from low power mode.

How to do it? Thanks.


Best regards,