MQX BSP Porting for MK61FN1M0VMJ12 using Processor Expert

[venkataprasad]

Hi team,

Environment :

     MQX 4.1

     IAR Embedded workbench

To create BSP for processor MK61FN1M0VMJ12, We followed the steps given in below doc

Freescale_MQX_4_1\doc\mqx\MQX_BSP_Porting_Example_User_Guide.pdf

steps:

     Cloning the BSP

     Installed PEx 10.4

     Setting up BSP for PEx with IAR EW-ARM for our processor 

     Build the MQX libraries

When I tried to test the BSP by executing a demo application which is created from "make_new_k60_mqx_project_iar.exe":

i am getting the following linker errors

Error[Li006]: duplicate definitions for "PE_low_level_init"; in "bsp_cm.o(bsp.a)", and "Cpu.o(bsp.a)"

Error[Li006]: duplicate definitions for "SR_lock"; in "bsp_cm.o(bsp.a)", and "Cpu.o(bsp.a)"

Error[Li006]: duplicate definitions for "SR_reg"; in "bsp_cm.o(bsp.a)", and "Cpu.o(bsp.a)"

Error[Li006]: duplicate definitions for "__low_level_init"; in "Cpu.o(bsp.a)", and "comp.o(psp.a)"

Please help me in resolving this issues.

[soledad]

Please check the below thread in our community web, it may helps,

https://community.freescale.com/docs/DOC-94248

In order to build a new BSP and PSP it is necessary:

1. Select a BSP and PSP that already exist. It is very important that you consider the factures and the core frequency; these should be very similar to the custom board. For example, if you want to create a BSP and PSP for a K20dx256z (100MHz) it is necessary to select the BSP and PSP for the twrk40x256 because the features and core frequency between both processors (k40 and k20) and the boards are very close.

In your case, if you need to change the core frecuency then you need to check the “How-to Change Default Clock Settings in Kinetis BSPs” document that you can find at the path:

C:\Freescale\Freescale_MQX_4_1\doc\tools\cw

2. Clone the select BSP using the BSP Cloning Wizard tool to clone the libraries (please check the video attached)

3. Another important thingh is selecting an existing BSP for the same pin version.

For example TWR-K60N512 144 pin version. MK60DZ10.h header file

c:\Freescale\Freescale_MQX_4_x\mqx\source\psp\cortex_m\cpu\MK60DZ10.h

covers also MK60DN256ZVLL10 device, in terms of memory map.

4.Mapping of functions to pins is specified in the BSP source file init_gpio.c:

c:\Freescale\Freescale_MQX_4_x\mqx\source\bsp\${CLONE_BSP_NAME}\init_gpio.c

5.Less flash memory size is to be modified in the linker command file. The location of the linker file is at
c:\Freescale\Freescale_MQX_4_x\mqx\source\bsp\<platform>\cw\*.lcf.

I hope this helps,

Have a great day,
Sol

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------