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Question asked by xuchao li on May 21, 2015
Latest reply on May 25, 2015 by Serguei Podiatchev

TOS is an internal delay in the feedback path for SDRAM_SYNC_IN with respect to the internal sys_logic_clk signal of the PC8245/MPC8241. The feedback trace length of SDRAM_SYNC_OUT to SDRAM_SYNC_IN should be shortened by 0.7 ns so that the impact of Tos can be reduced.

In AN2746(MPC8245/MPC8241 Memory Clock Design Guidelines: Part 2),They said : "Suppose the desired length for Tloop and the memory trace lengths (including clocks, data, and control signals) is about 0.32 nanoseconds (2 inches). Note that based on the MPC8245/MPC8241 hardware specifications document Tloop needs to be at least 0.7 nanoseconds (4.375 inches) less than the SDRAM clock trace lengths. Therefore, if the desired trace length for the SDRAM clocks is two inches (MPC8245/MPC8241 pin to SDRAM pin), then Tloop in that case cannot be more than zero inches. Furthermore, if Tloop is zero, the trace length for the SDRAM clocks needs to be about 4.4 inches to accommodate the full range of TOS"(page 8).This means is the trace of SDRAM_SYNC_IN should shorter then SDRAM_CLK by 0.7 ns.But in Unity X4 ( MPMC8240/MPMC8245 Schematics) they said :"Add 15cm (1.0ns) additional delay(SDELAY)to the SDRAM_SYNC_OUT - SDRAM-SYNC_IN path"(page 08).This means is the trace of SDRAM_SYNC_IN should longer then SDRAM_CLK by 1 ns. How should I design the trace of SDRAM_SYNC_OUT - SDRAM_SYNC_IN and SDRAM_CLK.



TOS是内部DLL的一个延迟。因为有这个的存在,按照硬件设计手册和时钟设计手册的说法,SDRAM_SYNC_OUT 到SDRAM_SYNC_IN 的走线应缩短(shortened)0.7ns,这你的缩短应该相对于在没有TOS时来说的,也可以理解为相对于SDRAM_CLK的走线长度来说的。按照这样的理解,SDRAM_SYNC_OUT 到SDRAM_SYNC_IN的走线,应该比SDRAM_CLK的短0.7ns。但是在Unityx4中的原理图注释中,给出的是SDRAM_SYNC_OUT 到SDRAM_SYNC_IN的走线,应该比SDRAM_CLK的长1ns,不知是我在什么地方理解错了,得到了矛盾的结果。望指点。