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MPC5748G: What is the purpose of PLLDIG.PLLCAL3 register (not present in MPC5748GRM) and how to configure it?

Question asked by Aleksandar Vinchev on May 21, 2015
Latest reply on May 26, 2015 by Peter Vlna

Value of this register is different in AN4830 and MPC5748GRM document...

According to MPC5748G header files (all versions, seen by me: V2.1.5, V2.1.12 and V3.0.00) this register contains 2 don't care bits, followed by 16 bits, specifying MFDEN, followed by 14 don't care bits:

  union {                          /* PLL Calibration Register 3 */
vuint32_t R;
struct {
  vuint32_t  :2;
  vuint32_t MFDEN:16;          /* Denominator fo fractional loop division factor. */
  vuint32_t  :14;
} B;

  } PLLCAL3;

 

Reading MPC5748GRM (on page 1200, PLLDIG.PLLCAL3.R = 0x09C3C000), MFDEN value is 0x24CF:

Reading mode_entry.c (PLLDIG.PLLCAL3.R = 0x00004062;  /* Set MFDEN a nonzero value (0x1 here) */) in AN4830SW package, MFDEN value is 0x0001 and next 14 reserved bytes are 0x0062.

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