. This has to do with the SDIO on the iMX6 and the SD1_CLK signal. From what I understand in chapter 22.214.171.124.4 DLL (Delay Line) in the Read Path; There is a delay line in figure 54-17 which show SDIO data being clock in on the same edge of the clock that goes to our SDIO module. Now we both know that there will be delay in the circuit. Our problem is that we are seeing incorrect data. If we look at the clock and data, we see that the rising edge of the clock is right in the middle of the data. Our software group has tried ever tap with no effect. So I believe that the Delay Line in the iMX6 is not working for us, most likely we are not setting up the registers correctly. Could you please explain how we should setup the register?
Some other things to note: We are using eCos, not Linux. We are looking at the Linux driver for guidance.