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Recommendations for write leveling delay values on i.MX6Q

Question asked by jschoen on May 20, 2015
Latest reply on May 24, 2015 by igorpadykov


Should the WRITE_LEVELING delay register values be set greater than the worst case delay value measured across boards?



The documents and discussions usually defer to using a model of the design to set the WRITE_LEVELING delay, but from our measurements using the DDR Stress Test, there is significant deviation board to board which may not align with a modeled design center.  Proposing to set delays in the shape of the average line but offset to where they are beyond the worst case delays