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How i.MX6SDL AXI_CLK_ROOT is created?

Question asked by Satoshi Shimoda on May 20, 2015
Latest reply on Sep 9, 2015 by gusarambula

Hi community,

 

I have a question about i.MX6SDL CCM.

I confirmed EIM ACLK(aclk_eim_slow) is created from AXI clock root (396MHz) in Which frequency is correct for i.MX6SDLACLK_EIM_SLOW_CLK_ROOT? .

However, according to the reset value of CCM_CBCDR register (chapter 18.6.6 in IMX6SDLRM Rev.1), AXI clock root seems to be created from PLL2 396MHz PFD.

In addition, in Figure 18-2, AXI_CLK_ROOT is same as DTCP_CLK_ROOT, but the default clock frequency of DTCP_CLK_ROOT is 270MHz in Table 18-3.

So I'm confused how AXI_CLK_ROOT is created.

Would you let me know what is correct?

 

 

Best Regards,

Satoshi Shimoda

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