AnsweredAssumed Answered

hdmi 1080p60 pixel clock

Question asked by Vadim Ignatov on May 19, 2015
Latest reply on May 26, 2015 by igorpadykov


I'm testing 1080p60 rendering on hdmi.

For 1080p60 the pixel clock must be set to 148.5MHz

From "iMX 6Series Plarform SDK v1.1.0" I found this code


   switch (pclk) {    // pixel clock 
        case 74250000: 
        case 148500000: 
            //clk output from 540M PFD1 of PLL3  
            HW_CCM_CHSCCDR.B.IPU1_DI0_CLK_SEL = 0;  // derive clock from divided pre-muxed ipu1 di0 clock 
            HW_CCM_CHSCCDR.B.IPU1_DI0_PODF = 5; // div by 6 
            HW_CCM_CHSCCDR.B.IPU1_DI0_PRE_CLK_SEL = 5;  // derive clock from 540M PFD 
            //config PFD1 of PLL3 to be 445MHz  

            printf("the hdmi pixel clock is not supported!\n"); 




The resulting clock is 445MHz / 6 = 74.2MHz for 1080p60 and 720p60.

Is that right ??? Why ipu1_di0 clock divider is not set to 3 for 1080p60 ?