Some questions about the MPC 8308 RDB(reference design board) Schematics

[pdwang]

Dear Sir:

      We are now developing a product based on MPC8308 RDB, but now we have some questions about the DDR part of MPC8308 RDB schematics. Please help us:

      1. The DDR2 SDRAM used in the RDB is HY5PS121621CFP-Y5 packaged in BGA 92, but I have read the datasheet of HY5PS121621CFP-Y5, it is packaged in BGA 84, there is no HY5PS121621CFP-Y5 packaged in  BGA92 at all.

      2. In the schematics, the DQ0 of MPC8308 DDR controller is connected with DQ6 of HY5PS121621CFP(U2), DQ1 of MPC8308 is connected with DQ3 of HY5PS121621CFP(U2), DQ2 of MPC8308 is connected with DQ7 of HY5PS121621CFP(U2),  etc.  Why does the MPC8308 connect with DDR2 SDRAM in this way? It seems that the DDR DQs are connected randomly. Normally, the DQ0 of CPU is connected with DQ0 of SDRAM, DQ1 of CPU is connected with DQ1 of SDRAM , accordingly.

      Waiting for your answer. Thank you very much!

[alexander_yakov]

1. Actually component in 84-pin package is soldered. These packages are pin compatible, the difference between 92-pin and 84-pin package is only in 8 supporting balls.

Please look the following application note from Micron:

DDR2 Package Sizes and Layout Requirements - Micron

In this document please look Page 3 (Figure 2).

2. This is done to simplify board layout. Actually, all memory cells within memory are identical, so it is not important where particular bit will be stored.

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