All LAB samples are showing 40MHz core, 20MHz BUS clock.
But I'd like to get 24MHz BUS clock for getting 115200bps UART.
Current I have TRK-KEA128.
Below is the block diagram of the ICS in the KEA128 (with a few extra details to make it more understandable):
The TRK-KEA128 that you have has an 8MHz crystal and so your setup will be using the FEE mode (FLL Engaged External), where the 8MHz external clock is divided to 31.25kHz (RDIV = /256). Since the FLL hs a fixed multiplication factor of 1280 it means that ICSOUTCLK is 40MHz and the bus clock is 20MHz (DIV1 is /1 and DIV2 is /2) due to the fact that the maximum speed of the bus/flash clock is 24MHz. It is not possible to get other clock rates higher than this using the 8MHz clock and FEE.
By using a divide by 11 from the bus clock you can run the UART at 113'636 Baud, which will be OK for 115'200 Baud (1.5% error).
If you require higher accuracy in this mode it is necessary to change the oscillator ito a value that gives a more accurate Baud.
If you however use the default FEI mode (the internal 37.5kHz as reference to the FLL), which is also the default out of reset, you more or less automatically have 48MHz ICSOUTCLK and a bus clock of 24MHz (set DIV2 to /2 an then BDIV to /1). A divide by 13 gives 115'384 Baud. However, the 37.5kHz reference will have more tolerance and drift over temperate that may actually give less accurate values.
Therefore you need to known that your BAUD accuracy rquirement is over the full operating conditions and decide whether to use the internal reference (saving an external crystal) or whether you need a high accuracy reference, which can be chosen to better suit the UART requirement if needed (4..24MHz crystal range is possible for the KEA128, as well as a 32kHz).
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