For my I.MX6 chip, I wrote a script for SDMA core which transferred data between the arm memory and the EIM Bus (FPGA on the other side). When I run the script, I monitored that each transfer duration is approximately 5 EIM clock cycles (address+1DWord Data + wait time) and the time gaps between these transfers are around 25 EIM clock cycles. So I thought I have a performance problem and I operated the same operation by a kernel thread in ARM CPU. The timings were the same! At the end of the day, I realized that the memory barrier in write&read operation caused this tremendous gap time between the operations. So, I used writel_relaxed&readl_relaxed operations, which does not call barrier functions, and the new gap time reduced to only 4 EIM clock cycles. So, I think the same problem occurs in the SDMA operations, because the gap durations are exactly the same.
In conclusion, I would like to know if there is any configuration&method to disable memory barrier in SDMA? I saw this gap problem in every SDMA function units (Peripheral&Burst) and every type of operations (prefetch, copy mode, read and write modes...).