Our partner have a question about i.MX53 ENGcm11038.
Please see their questions as below.
Please see ENGcm22038 description in IMX53CE (Rev.5).
It says "Due to non proper clock synchronization implementation,".
Our partner want to know this issue is a problem between what clock and what clock.
Would you let me know it?
We understansd EMI2.5 = EIM, so we believe this errata will be not occurred when EIM is not used, right?
Or EMI includes not only EIM but also DRAM and NAND interface?