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[solved] i.MX6Q has only two cores???

Question asked by Steffen Doster on May 12, 2015
Latest reply on May 20, 2015 by gusarambula

Hi again,

 

I noticed, that my Linux-Installation only recognizes two cpu-cores of the installed i.MX6Q, but I don't know why

 

Here is the configuration in my Device-Tree (copied from FSL SabreSD)

[CODE]

cpus {
#address-cells = <1>;
#size-cells = <0>;

 

cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
operating-points = <
/* kHz    uV */
1200000 1275000
996000  1250000
852000  1250000
792000  1150000
396000  975000
>;
fsl,soc-operating-points = <
/* ARM kHz  SOC-PU uV */
1200000 1275000
996000 1250000
852000 1250000
792000 1175000
396000 1175000
>;
clock-latency = ; /* two CLK32 periods */
clocks = <&clks IMX6QDL_CLK_ARM>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_STEP>,
<&clks IMX6QDL_CLK_PLL1_SW>,
<&clks IMX6QDL_CLK_PLL1_SYS>;
clock-names = "arm", "pll2_pfd2_396m", "step",
       "pll1_sw", "pll1_sys";
arm-supply = <&reg_arm>;
pu-supply = <&reg_pu>;
soc-supply = <&reg_soc>;
};

 

cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = ;
next-level-cache = <&L2>;
};

 

cpu@2 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = ;
next-level-cache = <&L2>;
};

 

cpu@3 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = ;
next-level-cache = <&L2>;
};
};  [/CODE]

 

Why does Linux see only two cores?

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