I am trying to debug some spurious imprecise external aborts (0x1406) (not really spurious, whenever they occur they occur at around 45 seconds from start).
I am trying to dump some information about the system state when the fault occured. I need to know -
if i.MX6 implements the auxiliary status register
as described by ARM manual -
Accessing the ADFSR and AIFSR
To access the ADFSR or AIFSR you read or write the CP15 registers with <opc1> set to 0, <CRn> set to c5,
<CRm> set to c1, and <opc2> set to:
• 0 for the ADFSR
• 1 for the AIFSR.
MRC p15,0,<Rt>,c5,c1,0 ; Read CP15 Auxiliary Data Fault Status Register
MCR p15,0,<Rt>,c5,c1,0 ; Write CP15 Auxiliary Data Fault Status Register
MRC p15,0,<Rt>,c5,c1,1 ; Read CP15 Auxiliary Instruction Fault Status Register
MCR p15,0,<Rt>,c5,c1,1 ; Write CP15 Auxiliary Instruction Fault Status Register
I also need to know the details of bit fields etc so that I can get some information about the faults.
The ARM manual describes the DFSR encoding as - Bit fields [11,10,3:0]. 11th bit -> read/write
However the DFSR value - 0x1406 has 12th bit set. Which according to manual is undefined. I need to know what is the implementation in i.MX6.