The K64F Sub-Family Data Sheet (Rev 3) p14 lists an IUART current adder of 66uA when MCGIRCLK is the clock source. The description of this parameter says it is "measured by placing the device in STOP or VLPS mode with selected clock source waiting for RX data at 115200 baud rate. Includes selected clock source power consumption."
I don't see anywhere in the Reference Manual (Rev 2) a way to allow the UART to continue to function while the CPU is stopped. Section 52.1.2 says the UART runs when the CPU is in Run Mode, that it may run or be halted when the CPU is in Wait Mode depending upon C1[UARTSWAI], and is halted when the CPU is in Stop Mode.
So what does that current adder spec refer to? Is there or isn't there a way to stop the CPU, and have the UART start it up again when a character is received? What I'd really like to do is use the 4MHz IRC for the UART, so that I can stop the crystal OSC module while the CPU is halted.